The present invention relates to delay circuits.
It is sometimes desirable to delay a signal, such as a clock signal by a predefined period of time. For example, in the double data rate (DDR) interface, the data signal (DQ signal) and the data strobe signal (DQS signal) (which may also herein be referred to as a clock signal) are sent edge aligned during a read operation. In such a context, it is desirable to phase shift the DQS signal by 90 degrees to sample the DQ signal at the center of the data valid window. To achieve the desired phase shift, a delay locked loop (DLL) is used to derive the optimum delay settings. Furthermore, it is sometimes desirable to achieve a fixed phase shift that is compensated across process, voltage and temperature (PVT) and other variations, particularly for circuits that are sensitive to PVT and other variations. Typically, the DLL includes current-starved delay cells that are tuned dynamically to an optimum delay setting to achieve the required phase shift on the DQS signal across PVT and other circuit variations.
In some cases, the delay circuit of the DLL is replicated in the input/output (I/O) banks of an integrated circuit (IC). More specifically, in some cases, the layout of the delay circuit is replicated in the layout of the vertical I/O (VIO) bank. Thereafter, the VIO bank layout is rotated to a horizontal orientation to create the layout for the horizontal I/O (HIO) bank. As a result, the layout of the delay circuit in the VIO bank has the same orientation as the layout of the delay circuit in the DLL, whereas the layout of the delay circuit in the HIO bank has a different orientation than the layout of the delay circuits in the DLL and the VIO bank.
FIG. 1 illustrates an IC with VIO and HIO banks. In FIG. 1, IC 100 includes core 101, DLL 110, VIO bank 150 and HIO bank 190. DLL 110 includes delay circuit 118, which includes current-starved delay cells orientated in the vertical direction. Delay cells include inverters or buffers for delaying signals. The inverters or buffers in turn include transistors. As used herein, the orientation of a delay cell refers to the orientation of the devices making up the delay cell, i.e., the inverters or buffers (or more specifically, the transistors making up the inverters or buffers) of the delay cell. VIO bank 150 includes VIO pin groups 120, 130, and 140 (which may also be referred to as VIO DQS data groups 120, 130, and 140). HIO bank 190 includes HIO pin groups 160, 170, and 180 (which may also be referred to as HIO DQS data groups 160, 170, and 180).
VIO pin group 120 includes pin circuits 121-125. VIO pin circuits 121, 122, 124, and 125 represent data pin circuits (e.g., DQ pin circuits), whereas VIO pin circuit 123 represents a clock pin circuit (e.g., a DQS pin circuit). VIO pin circuit 123 includes I/O pin (or pad) 126, buffer 127, delay circuit 128, and capture register 129. Delay circuit 128 has the same layout as delay circuit 118 of DLL 110. Moreover, the layout of delay circuit 128 is orientated in the same direction as the layout of delay circuit 118. As a result, delay cells in delay circuit 128 have the same orientation as delay cells in delay circuit 118. Additionally, DLL 110 drives the delay settings out to delay circuit 128. As a result, delay circuit 128 produces the required delay that was determined by DLL 110. The delayed clock signal from delay circuit 128 is also fed into the capture registers of VIO pin circuits 121, 122, 124, and 125.
As can be seen in FIG. 1, VIO pin groups 130 and 140 are similar to VIO pin group 120. As VIO pin groups 130 and 140 are similar to VIO pin group 120, they are not described in detail. It is to be noted that DLL 110 drives the delay setting of the delay circuits in VIO pin groups 130 and 140.
DLL 110 also drives the delay setting of the delay circuit in HIO pin groups 160, 170, and 180. The delay circuit in HIO pin group 160 has been referenced as delay circuit 168 in FIG. 1, whereas those of HIO pin groups 170 and 180 have not been referenced with a reference number. The layout of delay circuit 168 is orientated in a horizontal orientation. Similarly, the layouts of delay circuits in HIO pin groups 170 and 180 are also orientated in a horizontal orientation. Moreover, delay cells in delay circuit 168 are orientated in a horizontal orientation. Similarly, delay cells in delay circuits of pin groups 170 and 180 are also oriented in a horizontal, rather than a vertical, orientation.
FIGS. 2A, 2B, and 2C are block diagrams of the DLL, VIO, and HIO delay circuits, respectively, of FIG. 1. Moreover, FIGS. 2A-2C illustrate the relative orientation of the delay cells in the DLL, VIO, and HIO delay circuits of FIG. 1. In FIG. 2A, DLL delay circuit 118 includes delay cells 211, 212, 213, 214, 221, 222, 223, and 224 and multiplexer 230. Delay cells 211-214 are connected in series and delay the input clock signal CLKIN. The output of delay cell 214 is provided to multiplexer 230 and delay cell 221. Delay cells 221-224 are also connected in series and delay the delayed clock signal provided to them by delay cell 214. The output of delay cell 224 is provided to multiplexer 230. When IC 100 operates in high frequency mode, multiplexer 230 selects the delayed signal received from delay cell 214. Multiplexer 230 outputs the output clock signal CLKOUT for DLL delay circuit 118. On the other hand, when IC 100 operates in low frequency mode, multiplexer 230 selects the delayed signal received from delay cell 224. Delay cells 211-214 and 221-224 are oriented in a vertical direction as noted by the arrows therein in FIG. 2A.
As shown in FIG. 2B, VIO delay circuit 128 includes delay cells 241, 242, 243, 244, 251, 252, 253, and 254 and multiplexer 260. As can also be seen in FIGS. 2A and 2B, VIO delay circuit 128 is identical to DLL delay circuit 118. Therefore, VIO delay circuit 128 will not be described in further detail herein. It is to be noted that in VIO delay circuit 128, delay cells 241-244 and 251-254 are oriented in a vertical direction as noted by the arrows illustrated therein in FIG. 2B.
As shown in FIG. 2C, HIO delay circuit 168 includes delay cells 271, 272, 273, 274, 281, 282, 283, and 284 and multiplexer 290. In HIO delay circuit 168, delay cells 271-274 and 281-284 are oriented in a horizontal direction as noted by the arrows therein illustrated in FIG. 2C. Delay cells 271-274 are connected in series. Similarly, delay cells 281-284 are connected in series. The output of delay cell 274 is provided to multiplexer 290 and delay cell 281. The output of delay cell 284 is also provided to multiplexer 290. Multiplexer 290 outputs the output clock signal CLKOUT for HIO delay circuit 168. When IC 100 operates in high frequency mode, multiplexer 290 selects the delayed signal received from delay cell 274. On the other hand, when IC 100 operates in low frequency mode, multiplexer 290 selects the delayed signal received from delay cell 284.
As noted above, the delay cells in the delay circuits of the DLL 110 and VIO bank 150 have the same orientation, both being orientated in the vertical direction. On the other hand, as the delay cells in the delay circuits of the HIO bank 190 are orientated in the horizontal direction, they have a different orientation than those of DLL 110 and VIO bank 150. Delay cells in the layout with different orientation may be susceptible to channel length variation during the fabrication process, particularly if the process uses sub-micron technologies. This results in performance differences between delay cells with different orientations. This performance difference may herein be referred to as a poly-orientation effect. Thus, for example, delay cells in the DLL and the VIO bank may have a different performance from delay cells in the HIO bank. As a result, the optimum delay setting derived by the DLL will be optimum for the VIO bank as the delay cells in the DLL and VIO bank are drawn in the layout in a similar orientation. However, the delay settings determined in the DLL will not be optimum for the delay cells in the HIO bank which have a different orientation than those of the DLL. This results in different phase shifts for the DQS signals in the VIO and HIO banks. This may cause timing violations, particularly at high operating frequencies.